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Memory Controllers for Mixed-Time-Criticality Systems:Architectures, Methodologies and Trade-offs

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This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

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Availability

No copy data

Detail Information

Series Title

Embedded Systems

Call Number

-

Publisher

: ., 2016

Collation

XXVII, 202

Language

English

ISBN/ISSN

978-3-319-32093-9

Classification

NONE

Content Type

-

Media Type

-

Carrier Type

-

Edition

1

Subject(s)

Electronic Circuits and Systems
Processor Architectures
Electronics and Microelectronics
Instrumentation

Specific Detail Info

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Statement of Responsibility

Sven Goossens , Karthik Chandrasekar , Benny Akesson , Kees Goossens

Other Information

Cataloger

fandi

Source

-

Other version/related

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