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Memory Controllers for Mixed-Time-Criticality Systems:Architectures, Methodologies and Trade-offs

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template

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Detail Information
Series Title
Embedded Systems
Call Number
-
Publisher
: .,
Collation
XXVII, 202
Language
English
ISBN/ISSN
978-3-319-32093-9
Classification
NONE
Content Type
text
Media Type
computer
Carrier Type
online resource
Edition
1
Subject(s)
Electronic Circuits and Systems
Processor Architectures
Electronics and Microelectronics
Instrumentation
Specific Detail Info
-
Statement of Responsibility
Other Information
Cataloger
SUCI
Source
-
Validator
Taufik
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