Low-Noise Low-Power Design for Phase-Locked Loops: Multi-Phase High-Performance Oscillators

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Low-Noise Low-Power Design for Phase-Locked Loops: Multi-Phase High-Performance Oscillators

Feng Zhao - Personal Name; Fa Foster Dai - Personal Name;

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.

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Series Title: -
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Publisher: Cham : Springer Cham., 2015
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Language: English
ISBN/ISSN: 978-3-319-12200-7
Classification: NONE
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Subject(s): Speech and Image Processing
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Statement of Responsibility: Feng Zhao, Fa Foster Dai

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Cataloger: Kholif Basri
Source: https://link.springer.com/book/10.1007/978-3-319-12200-7
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Low-Noise Low-Power Design for Phase-Locked Loops Multi-Phase High-Performance Oscillators

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