Text

Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications

---

Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical and stress modeling methodologies is also presented in the book.

---

Availability

No copy data

Detail Information

Series Title

-

Call Number

-

Publisher

: Springer New York, NY., 2015

Collation

XVII, 322

Language

English

ISBN/ISSN

978-1-4939-1556-9

Classification

NONE

Content Type

text

Media Type

computer

Carrier Type

online resource

Edition

-

Subject(s)

Electronic Circuits and Systems
Electronics and Microelectronics
Instrumentation
Engineering Thermodynamics

Specific Detail Info

-

Statement of Responsibility

Shichun Qu, Yong Liu

Other Information

Cataloger

Yudi

Source

-

Validator

-

Other version/related

File Attachment

Comments

---

You must be logged in to post a comment