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Analysis and Design of Networks-on-Chip Under High Process Variation

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

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Detail Information
Series Title
-
Call Number
621.38 ELD a
Publisher
Cham, Switzerland : Springer Cham.,
Collation
XXI, 141
Language
English
ISBN/ISSN
978-3-319-25766-2
Classification
621.38
Content Type
text
Media Type
computer
Carrier Type
online resource
Edition
Ed. 1
Subject(s)
Electronic Circuits and Systems
Electronics and Microelectronics
Specific Detail Info
-
Statement of Responsibility
Other Information
Cataloger
umi
Source
https://link.springer.com/content/pdf/10.1007/978-3-319-25766-2.pdf?pdf=button
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